Great advances have been made in the last few years in semiconductor technology both in terms of new materials, new fabrication techniques and new semiconductor device structures. For example, geometrical features have become smaller, packing densities have become greater and fabrication techniques have improved.
This has been particularly true in the field of III-V semiconductor compound devices. Such devices promise greater speed in electronic circuits such as memories and logic circuits as well as greater bandwidth in amplifier circuits. Also, III-V semiconductor compounds are used in such optical devices as photodetectors, light-emitting diodes and lasers.
Particularly useful for such a developing technology are various fabrication procedures which are highly specific to certain materials and/or highly controlled so as to produce geometrical shapes with small dimensions. Indeed, small size and high packing density are highly desirable in many applications because it produces more functions per unit of chip area (large memories, logic circuits, etc.) and these desirable features require accurate, precise fabrication techniques.
A particular case in point is etching techniques used in fabricating devices with III-V semiconducting compounds. Here, uniform etching is desirable as well as high selectivity where one compound is to be etched in the presence of another compound. A typical plasma etching procedure for III-V semiconductor compounds is described in U.S. Pat. No. 4,397,711, issued to V. M. Donnelly et al, on Aug. 9, 1983.
Gaseous etching without a plasma is highly advantageous in a number of applications, particularly with semiconductor devices. Some of these advantages are minimum surface damage, better selectivity, simple to carry out and potential to etch a large number of devices simultaneously. Some of these advantages are discussed in U.S. Pat. No. 4,498,953, issued to J. M. Cook et al, on Feb. 12, 1985.